In recent years, the properties of the interfaces between adjacent layers within semiconductor devices have become a more important factor in optimizing performance. This is due, in part, to the ever decreasing size of the features of such devices.
For example, at the interface of the gate electrode layer and the gate dielectric layer, a large dipole is often formed due to the differences in the properties of the two materials used. This is typical in both silicon-based and germanium-based devices. This dipole may adversely affect performance and may indicate a less than ideal bond formed between the two materials.